Project A.L.L.B.I.N.

Fast Data Sampler


Design goals

1) The European Radio Astronomy Club (ERAC) has a need for running fast data samplers when processing RF signals from radio telescopes. There is basically no upper limit for sampling speed and therefore a first priority design goal is to reach as high as possible sampling rates.

2) The target signals come from weak sources which are merged with noise. A major design goal is to maintain the signal-to-noise ratio (S/N) on an as high as possible level while doing fast data sampling. Therefore the analog part and the digital part of the solution have to be build into separate shielding boxes.

3) The ERAC community units amateurs and professional radio astronomers who run on quite different budgets for the equipment. While striving to meet highest technical figures the solution should allow to build devices from a small budget as well as highest performance solutions on higher budgets.


Solution proposal

An ERAC sampling solution will be based on a defined connector which brings the ADC(s) and the data capture board together. The connector is named "ERAC Fast Sampler Connector (EFSC) and it is identical to the J1 connector defined by Analog Devices for ADC evaluation boards. This allows to select a concrete sampler out of about 100 boards that are offered by Analog devices for different technical requirements. The reason not to call the connector same as the original specification is to have an opportunity to define currently unused pins on the 120-pin connector accordingly to ERAC's needs as well as to define smaller pin headers that will be compliant with the full 120-pin header.

A preferred data sampling board is currently the Spartan-3A DSP 1800A evaluation board from Xilinx. This board offers all features for sampling data at 100 MegaSamples/sec. and higher while allowing for a data transfer to a host computer at more than 100 MBytes/sec. on a Gigabit Ethernet connection.

That board has been selected in a joined effort from Analog Devices and AVNet as a solution for demonstrating outstanding features of Analog Devices' ADC circuits. A sample is available for an ADC/FPGA project which can be compiled using Xilinx's free development environment for FPGAs. Thus interested amateurs can start directly to learn from a running sample project provided by professional developers who aim at lowering the entry level to a DSP on FPGA project to a minimum.

There is also a low-cost variant in the order of 50 total cost available which is based on the UUUSB board from Marko Cebokli along with a suitable ADC. Such a low cost solution is achievable for amateurs if they ask for sample ADC circuits as well as for a sample USB circuit as it is used on the UUUSB board. A PCB has to be designed and manufactured in this case in order to connect a selected ADC to the UUUSB board.

The proposed ERAC sampler solution allows for a couple of variants which are shown in the following and that all are based on the chosen pin layout for the connector. In order to support all variants, there have been sub-connectors defined with 60 pins and with 40 pins respectively which allow to connect a single ADC with/without SPI to a data sampling board. A smaller variant of a header is always compatible to a connector with a higher pin number.


120-pin header


Dual channel solutions (with SPI)


Single channel solutions (with SPI)


Single channel solutions (basic, without SPI)


ADC board with EFSC to EXP (FPGA) connector board


Spartan-3A DSP 1800A


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